In complex photolithographic equipment, the individual subsystems are coordinated with one another to accurately position a substrate (e.g., a silicon wafer) on an exposure stage so that a circuit pattern on a mask can be accurately exposed onto a desired location of the wafer. However, prior to this, the wafer may have undergone a large number of processes which result in considerable flaws in the wafer mainly as low roundness, an inconsistent radius and tolerances in the notch shape. Additionally, depending on the adopted TSV (Through Silicon Via) packaging processes, the resulting wafers may have various geometric issues such as adhesive bumps and edge burrs. Therefore, the complexity of wafer edge geometry places a great challenge on wafer pre-alignment. Whether the wafer can be placed on the exposure stage within a given deviation range will have a directly impact on the performance of the photolithographic equipment. Thus, wafer pre-alignment plays a vital role and affects the wafer placement accuracy.
Wafer centering is a process to adjust the position of a wafer relative to that of a wafer stage so as to align a center of the wafer with a predetermined position (e.g., a center) of the stage, while wafer orientation is a process to accurately determine the positions of notches or marks on the centered wafer and, based thereon, rotate the wafer so that it is oriented at a given angle with respect to the wafer stage. The existing wafer pre-alignment methods involve identifying the notches at the edge of the wafer by means of image capture devices. However, the identification requires binarization of the captured images, which imposes critical requirements on the clarity of the images, making the methods not universal.